The invention generally relates to a semiconductor device. More particularly, the invention relates to a semiconductor device including a storage node and a method of fabricating the same.
Generally, a Dynamic Random Access Memory (DRAM) cell includes a capacitor for storing charges that represent information to be stored and a transistor for addressing the stored charges in the capacitor. The transistor formed over a semiconductor substrate also includes a gate that controls a current flowing between source/drain regions. Charges stored in the capacitor can be accessed through the transistor. Capacitance C refers to the amount of electric charge stored in a capacitor. As the capacitance becomes larger, more information can be stored.
The capacitance is represented by Equation 1.
                    C        =                  ɛ          ⁢                                          ⁢                      A            d                                              Equation        ⁢                                  ⁢        1            
∈ is a dielectric constant determined by different types of dielectric films disposed between two electrodes, d is a distance between the two electrodes, and A is an effective surface area of the two electrodes. Referring to Equation 1, the capacitance of the capacitor can be increased by increasing ∈, reducing d and/or increasing A. The electrode structure of the capacitor may be changed to be three-dimensional such as a concave structure or a cylindrical structure, thereby increasing the effective area of the electrodes.
A concave-structured capacitor includes a hole formed in an interlayer insulating film where a lower electrode is formed. A lower electrode of the capacitor is formed in the hole. A dielectric film and an upper electrode are deposited over the lower electrode. Due to the high-integration of semiconductor devices, it is difficult to secure a sufficient capacitance required in each cell of a limited cell area even in the concave-structured capacitor. As a result, a cylinder-structured capacitor has been developed to provide a surface area that is larger than the surface area of the concave-structured capacitor.
The cylinder-structured capacitor includes a hole formed in an interlayer insulating film where a lower electrode region of the capacitor is defined. A lower electrode of the capacitor is formed in the hole, and the interlayer insulating film is removed, which is called as a dip-out process. A dielectric film and an upper electrode are deposited over the residual lower electrode. The cylinder-structured capacitor can use the inner and outer surfaces of the lower electrode as an effective surface area, resulting in a capacitance that is larger than that of the concave-structured capacitor.
However, misalignment may occur in the capacitor due to the lack of an overlap margin between a storage node and storage node contact plug. As a result of the misalignment during an etching process for forming a storage node region, the interlayer insulating film, which electrically isolates storage node contact plugs from each other, is also etched. In addition, a bit line disposed below the interlayer insulating film is exposed due to the etched interlayer insulating film. As a result, a failure in self-align contact (SAC) etching may occur.